1. Field of the Invention
Embodiments of the present invention generally relate to methods for forming semiconductor devices. More particularly, embodiments of the present invention generally relate to methods for forming a molecular dopant layer on a semiconductor substrate.
2. Description of the Related Art
Reliably producing submicron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the miniaturization of circuit technology is pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. Recently, complementary metal oxide semiconductor (CMOS) FinFET devices have been widely used in many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed thereover. A gate electrode is then formed over and along side of a portion of the fin devices utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of FinFETs include reducing the short channel effect and providing higher current flow.
Currently, an ion implantation process is often used to provide dopants into desired regions of the substrate, referred to as a beamline process. In the beamline process, various substrate tilting is often used to ensure that sidewall surfaces of the features formed on the substrate are satisfactorily implanted. However, at high substrate tilt angles, the side walls of closely packed structure may not fully exposed to the ion beam, which undesirably leads to non-uniform/non-conformal distribution of the dopant material. This non-uniform/non-conformal doping profile may create issues including non-uniform device turn on voltages.
Therefore, there is a need for an improved conformal doping process for FinFET device fabrication.